Exemplary embodiments of the present invention relate to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device with a side junction region.
In general, a horizontal gate has a horizontal channel. Recently, a vertical gate structure with a vertical channel is being developed to increase a net die. In a DRAM, each cell with a vertical gate structure may include an active region including a body and a pillar, a buried bit line, and a vertical gate (or a vertical word line). Here, the pillar may be a portion of the body. For example, the buried bit line is buried in a trench between the bodies of active regions, and the vertical gate is formed at a sidewall of the pillar of the active region over the buried bit line. The buried bit line may be buried between adjacent active regions, so that two cells are adjacent to one buried bit line. A one-side-contact (OSC) process, which is performed to insulate one of adjacent active regions and form a contact at the other, may be applied to drive one cell per one buried bit line. The OSC process is used to form a junction region at a sidewall of the active region, and the junction region is electrically connected to the buried bit line.
The OSC process is performed to expose a portion of one sidewall of the active region. Thereafter, a dopant is ion-implanted into the portion of the one sidewall of the active region to form the side junction region. Also, an annealing process may be performed to form the side junction region.